H.264 Baseline video encoder implementation and optimization on TMS320DM642 digital signal processor /

Official URL: http://risc01.sabanciuniv.edu/record=b1161868 (Table of Contents)

Digital video encoding plays an important role in many applications such as digital surveiance systems, video conference systems as wel as digital TV. In this thesis. a H.264 baseline encoder is implemented on Texas Instruments TMS320DM642 digital signal processor. The TMS320DM642 is a high-performance digital media processor with 2-level memory/cache hierarchy and very-long-instruction-word (VLIW) architecture. The proposed encoder system consists of almost al parts of standard H.264 baseline encoder except quarter-pel motion compensation and error resiliency tools such as Arbitrary Sice Ordering (ASO) and Flexible Macroblok Order (FMO). Instead of quarter-pel motion compensation, integer-pel motion estimation and compensation for both Luminance and Chrominance samples is implemented. The complete H.264 encoder system is verified to work on both computer and DM642 EVM (Evaluation Module) platform. Basicaly, the encoder takes the input of a QCIF video sequence (YUV) and converts it to the standard compressed H.264 AnnexB fie format. The encoder is fuly compliant with the standard H.264 JM Decoder. The reconstructed video, which is exactly the same with the output of the standard JM H.264 decoder, is being displayed on a TV screen. In addition, by making use of the TI development tools. performance of the complete encoder system is anayzed for real-time applications. Finaly, memory optimization, code optimizations and compier optimizations are applied to the encoder for higher performance. The proposed H.264 encoder is able to encode, display and store 26.7 QCIF frames per second.