Design and realization of a high-speed 12-bit pipelined analog-digital converter IP block

Official URL: http://risc01.sabanciuniv.edu/record=b1078882 (Table of Contents)

This thesis presents the design, verification, system integration and the physical realization of a monolithic high-speed analog-digital converter (ADC) with 12-bit accuracy. The architecture of the ADC has been realized as a pipelined structure consisting of four pipeline stages, each of which is capable of processing the incoming analog signal with 4-bit accuracy. A bit-overlapping technique has been employed for digital error correction between the pipeline stages so that the influence of possible errors that occur during analog signal processing can be minimized. The entire circuit architecture is built with a modular approach, consisting of identical blocks organized into an easily expandable pipeline chain. All analog as well as digital sub-blocks of the ADC architecture presented in this work operate on a single clock signal (and its inverse), which significantly simplifies the design while ensuring a more robust performance. Other important features of this ADC include small area, single power supply, low power consumption, capability to operate at very high sampling clock rates, and the ability to handle a wide range of input signal amplitudes. The analog processing modules were designed using single-ended signals and the single-ended building blocks (as opposed to differential signals and building blocks) for simplicity. The ADC architecture was realized using a conventional 0.18 micron digital CMOS technology (Foundry: UMC), which ensures a lower overall cost and better portability for the design. The ADC architecture presented in this work is capable of operating at sampling frequencies of up to 200 MHz, and still can achieve the nominal bit-resolution that was intended for 12-bit accuracy. The entire circuit is designed with single 1.8 V power supply. The maximum range of the input signal amplitude that the ADC can handle is 1.6 Vpp, with 1.8 V supply voltage. The input signal range as well as the operating points of critical components can be adjusted externally using dedicated control pins. The overall power consumption is estimated as 67.5 mW at 200 MHz sampling rate. Each 4-bit pipeline stage consists of a 4-bit flash A/D converter, a fully capacitive multiplying DAC (MDAC) and the corresponding digital encoding circuitry. The overall silicon area of the ADC is approximately 0.25 mm2. The ADC architecture presented in this thesis is intended as a state-of-the-art data converter for very high-speed applications such as digital video transmission or high bandwidth wireless communication needs. It can be used either as a stand-alone single-chip unit, or as an embedded IP block that can be integrated with other modules on chip.