Capacity allocation with machine duplication in semiconductor manufacturing

Official URL: http://dx.doi.org/10.1002/nav.20104

The manufacturing process for a computer chip is complex in that it involves a large number of distinct operations requiring a substantial lead-time for completion. Our observations of such a manufacturing process at a large plant in the United States led us to identify several tactical and operational problems that were being addressed by the production planners on a recurring basis. This paper focuses on one such problem. At a tactical level, given a demand forecast of wafers to be manufactured, one specific problem deals with specifying which machine or machine groups will process different batches of wafers. We address this problem by recognizing the capacity limitations of the individual machines as well as the requirement for reducing operating and investment costs related to the machines. A mathematical model, which is a variation of the well-known capacitated facility location problem, is proposed to solve this problem. Given the intractability of the model, we first develop problem specific lower bounding procedures based on Lagrangean relaxation. We also propose a heuristic method to obtain "good" solutions with reasonable computational effort. Computational tests, using hypothetical and industry-based data, indicate that our heuristic approach provides optimal/near optimal solutions fairly quickly.