Development of process, voltage and temperaturevariation aware highly energy-efficient deepneural networks with high inference accuracyfor internet-of-things applications

Artificial intelligence (AI models have improved with advancements in hardware,processing large datasets crucial for daily applications. The Internet-of-Things (IoT)enhances AI usage but brings challenges like bandwidth overhead, latency, and cyberthreats. Edge computing and fast, energy-efficient hardware, like application-specificintegrated circuit DNN accelerators, are essential solutions for IOT devices.To further enhance energy efficiency, voltage reduction on power supplies is a viablemethod, despite causing timing errors that DNNs might tolerate due to theirinherent nature. Extensive MAC operations also lead to significant switching activity,potentially generating noise on the chip’s power lines. In this thesis, processvoltage temperature (PVT) aware probabilistic timing error model is developed anddemonstrated to find error probability due to voltage and temperature noise. Byutilizing this model, bit error probability can be calculated without relying on thetime-consuming Monte Carlo (MC) simulations, thus the analysis time of the digitalhardware is significantly reduced. By observing the inference accuracy of a DNNmodel through the introducing of bit errors to its layers, designers can optimizepower consumption by employing dynamic voltage scaling based on layer importance. A 16x16 systolic MAC array accelerator was designed using 65nm CMOS technologyto verify the model. Single MAC unit is analyzed for timing error probability andresult is compared with MC simulations. The model demonstrated decent accuracyand was approximately 808 times faster than MC simulations (1500 sample), allowingfor rapid observation of voltage reduction effects on the accelerator in terms oftiming error probability.