Effıcient Hevc And Vvc Video Compression Hardware Designs

Official URL: https://risc01.sabanciuniv.edu/record=b3402310

Digital video usage has significantly increased in recent years. Since both the spatial and temporal resolutions of videos increased, new video compression standards such as High Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) are developed to achieve higher compression efficiency. VVC has higher compression efficiency than HEVC at the cost of higher computational complexity. Approximate computing can be used to reduce the computational complexity of error tolerant applications such as video compression. Dedicated hardware implementations are required for real time video compression. In this thesis, we propose efficient exact HEVC and VVC hardware implementations. To reduce the computational complexity of HEVC and VVC algorithms, we propose approximate VVC fractional interpolation (FI) filters, HEVC two-dimensional (2D) discrete cosine transform (DCT) using approximate constant multiplication, and approximate VVC affine motion estimation (AME). We propose efficient approximate HEVC and VVC hardware implementations using approximate algorithms and approximate hardware. In this thesis, approximate VVC FI filters are proposed. The proposed approximate filters reduce computational complexity of VVC FI at the expense of very small quality loss. Three VVC FI hardware implementing the proposed approximate VVC FI filters are also proposed. A novel VVC FI hardware using memory based constant multiplication is proposed. A new technique called decomposed coefficients is proposed for implementing HEVC FI (HFI) and VVC FI (VFI). The proposed technique decomposes the coefficients of FIR filters such that the number of additions is reduced. A new approximate constant multiplication technique is used to propose a HEVC 2D DCT hardware, in which common constant multiplications are calculated once so that the number of multiplications is reduced. The first FPGA implementations of VVC FI and HEVC fractional motion estimation (FME) using an HLS tool in the literature are proposed. Novel FPGA implementations of HEVC DCT algorithm using an HLS tool are proposed. An approximate VVC AME hardware is proposed using a proposed approximate absolute difference (AD) hardware, approximate adder tree, and sub-sampling.