Design of voltage controlled oscillator and integer-N divider for 5G frequency synthesizer application

Official URL: https://risc01.sabanciuniv.edu/record=b3078186_(Table of contents)

In 5G systems, transceivers require LO signals at mmWave frequencies with low phase noise to meet the SNR required for data rates of multiple gigabits per second. In addition, the PN causes detection errors, causing internal noise, and further performance degradation. The primary on-chip solution for generating an LO signal is a phase-locked loop used as a frequency synthesizer to generate a frequency range from a given reference that meets the required noise performance. The VCO is the integral block that affects the overall performance the most among the blocks that make up the phase locked loop. This thesis focuses on designing the VCO and integer-N frequency divider circuits for Type-II fourth order integer-N PLL-based frequency synthesizer realized in IHP SG13S technology. Two different VCOs that have 3 and 4-bit capacitor banks are realized. Both designs utilize the varactor linearity control method to exploit the tuning range and the quality factor relation. The measured 3-bit VCO achieves a tuning range between 9.46 to 11.092 GHz and has a phase noise of -114.42 dBc/Hz at 1MHz offset at the center frequency with a power consumption of 28.7 mW and 2.38 mm2 area. The simulation results of the 4-bit VCO are a 9.5 to 12.02 GHz tuning range and -116.2 dBc/Hz noise at the center frequency, with a power consumption of 30mW and 2.33 mm2 area. Furthermore, the design of the divider is examined, and modifications to improve the area and power consumption are done, which performs the required division VCO output to 100MHz. Finally, the realized PLL has a simulated phase noise of -108.7 dBc/Hz and an area of 4.67 mm2.