RISC-V based triple modular redundant CPU design for space applications

Official URL: https://risc01.sabanciuniv.edu/record=b3076401_(Table of contents)

Fault-tolerant processors are essential for spacecraft because of the high-radiation environment of space. While the required reliability can be achieved by using specialized radiation-hardened processors, the cost is prohibitive. With the advent of CubeSats, low-cost spacecraft started to increasingly rely on non-radiation-hardened commercial-off-the-shelf components. Triple-modular redundancy can be applied to existing processor designs to increase reliability without using costly radiationhardened ASIC processes or FPGAs. In this thesis, we demonstrate a conceptual fault-tolerant RISC-V processor by applying coarse-grain TMR to the open-source PicoRV32 core. To implement coarse-grain TMR, we attached word voters to the memory bus without modifying the internal structure of the processors. Using word voters increases error detection capability by revealing multi-module errors which can be masked by conventional bit-by-bit voters. Moreover, we propose a TMR controller module that can relay fault conditions to software and reset the CPUs. The module can help software to facilitate fault recovery procedures. Finally, we compare the synthesis results of our demonstration system with similar applications that use finer-grain TMR implementation. Our preliminary experiments show that the proposed coarse-grain TMR architecture can be used to protect ready-made IP cores with less development effort, which can be useful for low-cost space applications.