Efficient HEVC and VVC motion estimation hardware

Official URL: https://risc01.sabanciuniv.edu/record=b2579290_(Table of contents)

The significant increase in digital video usage and spatial and temporal video resolutions, has led to the development of new video coding standards, which can compress more without causing quality loss. HEVC and VVC are the two latest video coding standards. VVC is the most recent standard and it is more computationally complex than HEVC. Motion estimation (ME) is used in these standards to remove temporal redundancies between successive video frames. ME accounts for at least 50% and as much as 70% of the total encoding time in both these standards. Approximate computing is an emerging technique to design efficient hardware for error-tolerant applications such as video coding. In this thesis, an efficient HEVC ME hardware is proposed. An approximate adder, suitable for absolute difference operation, is proposed and integrated to this HEVC ME hardware. Detailed comparison of several approximate circuits including the proposed approximate adder and traditional bit truncation technique for HEVC ME is presented. The proposed approximate adder achieved up to 10% power reduction in ME hardware while providing better quality than the other approximate circuits. An efficient hardware for translational VVC ME is also proposed. It is the first VVC ME hardware in the literature. The proposed hardware reduces the memory accesses significantly by using an efficient data access and reuse method. It uses a novel adder tree to minimize hardware area while meeting real-time video encoding requirements. It is capable of processing up to 30 4K video frames per second. An efficient approximate sum of absolute differences (SAD) hardware is proposed for FPGAs. It utilizes the unused LUT inputs of an FPGA to reduce area and power consumption while providing an almost accurate result. The proposed approximate SAD hardware uses up to 20% less LUTs and consumes up to 38% less power than the smallest and lowest power-consuming approximate SAD hardware in the literature, respectively. The proposed SAD hardware can be used in HEVC and VVC ME hardware. Finally, a methodology is proposed for designing low error efficient approximate adders for FPGAs. Two approximate adders for FPGAs are designed using the proposed methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). LEADx has lower mean square error than the approximate adders in the literature. APEx is the smallest and lowest power consuming FPGA-based adder in the literature. These approximate adders are integrated to ME in HEVC software encoder. LEADx provided better quality than the other approximate adders for HEVC video coding.