Efficient hardware implementations for lattice-based cryptography primitives

Official URL: https://risc01.sabanciuniv.edu/record=b2579255_(Table of contents)

Lattice-based cryptography has gained a tremendous amount of attention in the last decade due to two main reasons: (i) being projected to be resistant against the attacks by quantum computers and (ii) enabling homomorphic encryption (HE) which allows arithmetic operations on the encrypted data. Despite its theoretical advantages, it lacks efficient and practical implementations due to its high computational complexity, especially in the context of HE. In this dissertation, our main objective is to design and implement high-performance and efficient hardware solutions for lattice-based cryptosystems. To that end, we propose a collection of efficient and flexible hardware accelerators for lattice-based HE and post-quantum cryptography (PQC) schemes. Firstly, we present two different hardware architectures for Number Theoretic Transform (NTT) which is one of the most fundamental building blocks of lattice-based cryptography with several optimizations. The proposed architectures are used in a CPU-FPGA framework providing fast communication via PCI Express link to accelerate the encryption and decryption operations of the Brakerski/Fan-Vercauteren (BFV) HE scheme. Secondly, we present a run-time configurable NTT-based polynomial multiplication architecture that supports a set of algorithm parameters frequently used in lattice-based cryptosystems. Thirdly, we design and implement a high-performance hardware architecture that performs the homomorphic multiplication and relinearization operations for the full RNS variant of the BFV HE scheme on FPGA. The proposed architecture outperforms the highly-optimized Microsoft SEAL HE library by more than an order of magnitude. Fourthly, we design and implement one of the earliest polynomial multiplication architectures of the CRYSTALS-Kyber PQC scheme, which is one of the finalists in NIST’s PQC standardization process, for the FPGA platform in the literature. Finally, we investigate two different design methodologies for generating flexible NTT hardware along with a comprehensive analysis. The first method uses a compile-time configurable parametric NTT hardware generator while the second method presents the high-level synthesis approach.