High resolution, process and temperature compensated phase shifter design using a self generated look up table

Official URL: http://risc01.sabanciuniv.edu/record=b1640591 (Table of Contents)

Phase resolution is one of the most important parameters in phased array RADAR determining the precision of antenna beam direction and side-lobe level. Especially, in tracking applications the antenna directivity should be high and side-lobe levels must be low in order to abstain from the signals of Jammers. Phase shifters (PS) set phase resolution and directivity; therefore, they are the key components for phased arrays. Among the PS topologies, vector sum type comes forward due to its significant advantage over the other design techniques, in terms of insertion loss, phase error, area and operation bandwidth. However, in design of vector sum type PS, phase and amplitude errors in vectors, and phase insertion of variable gain amplifiers degrades the phase resolution performance of the PS. In order to overcome these issues and improve bit resolution (reduced phase step size and lower phase error while covering 360° phase range), and improve the tolerance on process - temperature variations, the proposed solution in this thesis is the design of a calibration circuit consisting of Power detector (PD), Analog to Digital Converter (ADC) and a Digital Processing Unit (DPU). The main objective of the calibration loop is the generation of a Look up Table (LUT) for target frequency band and at operating temperature. With this technique, the first 7-bit Phase shifter is designed in SiGe- BiCMOS technology, which also has highest fractional bandwidth in literature.