High performance image demosaicing hardware designs

Official URL: http://risc01.sabanciuniv.edu/record=b1558964 (Table of Contents)

Most digital cameras capture only one color channel (red, green, or blue) per pixel, because capturing three color channels per pixel would require three image sensors which increases the cost of digital cameras. Therefore, only one image sensor is used, and images pass through a color filter array (CFA) before being captured by the image sensor. Bayer pattern is the most commonly used CFA pattern in digital cameras. Demosaicing is the process of reconstructing the missing color channels of the pixels in the color filtered image using their available neighboring pixels. There are many image demosaicing algorithms with varying reconstructed image quality and computational complexity. In this thesis, high performance hardware architectures are designed for three high quality image demosaicing algorithms, and the proposed hardware architectures are implemented on FPGA. A high performance hardware architecture for Effective Color Interpolation (ECI) demosaicing algorithm is proposed. A modified version of Enhanced ECI demosaicing algorithm and a high performance hardware architecture for this image demosaicing algorithm are proposed. A hybrid ECI and Alternating Projections demosaicing algorithm and a high performance hardware architecture for this image demosaicing algorithm are proposed. The proposed hardware architectures are implemented using Verilog HDL. The Verilog RTL codes are mapped to Xilinx Virtex 6 FPGA. The proposed FPGA implementations are verified with post place & route simulations. They are capable of processing 160, 118, and 119 full HD images per second.