A High permormance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for H.264 video coding

Yalçın, Sinan and Ateş, Hasan F. and Hamzaoğlu, İlker (2005) A High permormance hardware architecture for an sad reuse based hierarchical motion estimation algorithm for H.264 video coding. In: 15th Int Conf on Field Programmable Logic and Applications, Nice

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Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264 / MPEG4 Part 10 video coding. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 68 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640x480) or 82 CIF frames (352x288) per second.
Item Type: Papers in Conference Proceedings
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Natural Sciences
Depositing User: Sinan Yalçın
Date Deposited: 17 Dec 2006 02:00
Last Modified: 26 Apr 2022 08:33
URI: https://research.sabanciuniv.edu/id/eprint/1239

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