Items where Author is "Kulse, P."

Article

Barıştıran Kaynak, Canan and Yamamoto, Yuji and Goeritz, A. and Korndoerfer, F. and Zaumseil, P. and Kulse, P. and Schulz, K. and Wietstruck, M. and Shafique, Atia and Gürbüz, Yaşar and Kaynak, Mehmet (2018) High performance thermistor based on Si1-xGex/Si multi quantum wells. IEEE Electron Device Letters, 39 (5). pp. 753-756. ISSN 0741-3106 (Print) 1558-0563 (Online)

Papers in Conference Proceedings

Baristiran Kaynak, C. and Yamamoto, Y. and Göritz, A. and Korndörfer, F. and Zaumseil, P. and Kulse, P. and Schulz, K. and Fraschke, M. and Marschmeyer, S. and Wolansky, D. and Wietstruck, M. and Shafique, Atia and Gürbüz, Yaşar and Kaynak, Mehmet (2018) Si1-xGex/Si MQW based uncooled microbolometer development and integration into 130 nm BiCMOS technology. In: 8th Symposium on SiGe, Ge, and Related Compounds: Materials, Processing, and Devices - AiMES 2018, ECS and SMEQ Joint International Meeting, Cancun, Mexico

Kaynak, C. Baristiran and Yamamoto, Y. and Göritz, A. and Korndörfera, F. and Zaumseil, P. and Kulse, P. and Schulz, K. and Wietstruck, M. and Costina, I. and Shafique, Atia and Gürbüz, Yaşar and Kaynak, Mehmet (2018) Pixel resistance optimization of a Si0.5Ge0.5/Si MQWs thermistor based on in-situ B doping for microbolometer applications. In: Infrared Technology and Applications XLIV 2018, Orlando, FL, USA

Wietstruck, M. and Marschmeyer, S. and Lisker, M. and Kruger, A. and Wolansky, D. and Fraschke, M. and Kulse, P. and Goritz, A. and Inac, M. and Voss, T. and Mai, A. and Kaynak, Mehmet (2018) Through-Silicon Via process module with backside metallization and redistribution layer within a 130 nm SiGe BiCMOS technology. In: IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore

Wietstruck, M. and Marschmeyer, S. and Voß, T. and Inac, M. and Lisker, M. and Krüger, A. and Wolansky, D. and Kulse, P. and Schulz, K. and Katzer, J. and Göritz, A. and Mai, A. and Kaynak, Mehmet (2017) 200 mm silicon wafer with buried 3D etchstop layer for flexible-sized via-middle tsvs in a CMOS/BiCMOS technology (200 mm silizium wafer mit vergrabenen 3D-atzstoppschichten für flexible via-middle TSVs in CMOS/BiCMOS technologien). In: MikroSystemTechnik Kongress 2017: MEMS, Mikroelektronik, Systeme - MikroSystemTechnik Conference 2017: MEMS, Microelectronics, Systems, Munchen