Through-Silicon Via process module with backside metallization and redistribution layer within a 130 nm SiGe BiCMOS technology

Wietstruck, M. and Marschmeyer, S. and Lisker, M. and Kruger, A. and Wolansky, D. and Fraschke, M. and Kulse, P. and Goritz, A. and Inac, M. and Voss, T. and Mai, A. and Kaynak, Mehmet (2018) Through-Silicon Via process module with backside metallization and redistribution layer within a 130 nm SiGe BiCMOS technology. In: IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore

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Abstract

The development of a Through-Silicon Via process module within a high performance SiGe BiCMOS technology is demonstrated. The TSV technology module including both the TSV fabrication process itself, the temporary wafer bonding for BiCMOS thin wafer handling and the thin wafer backside processing is developed on 8-inch wafer level and the optimization of the different process steps are explained. This process module is fully compatible with the qualified SiGe BiCMOS technology environment which enables very uniform and reliable TSV backside fabrication adding new functionalities into IHPs high performance SiGe BiCMOS technologies applicable for thin wafer applications and 3D heterogeneous integration.
Item Type: Papers in Conference Proceedings
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: Mehmet Kaynak
Date Deposited: 03 Jun 2023 20:01
Last Modified: 03 Jun 2023 20:01
URI: https://research.sabanciuniv.edu/id/eprint/45830

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