Low-Power IEEE 802.11n LDPC Decoder Hardware

In this paper, we present a low power hybrid low-density-parity-check (LDPC) decoder hardware implementing layered min-sum decoding algorithm for IEEE 802.11n Wireless LAN Standard. The LDPC decoder hardware, which has 27 check node datapaths and 24x162 variable node memory, is implemented in Verilog HDL and verified to work correctly in a Xilinx Virtex II FPGA. For 648 block length and 1/2 code rate, on a Xilinx Virtex II FPGA, the LDPC decoder hardware implementation works at 83.5 MHz and it can process 60.68 Mbps. For 648 block length and 5/6 code rate, on a Xilinx Virtex II FPGA, the LDPC decoder hardware implementation works at 71.5 MHz and it can process 113.78 Mbps. The power consumption of the implementation on a Xilinx Virtex II FPGA is estimated as 2052 mW for 648 block length and 1/2 code rate and 1989 mW for 648 block length and 5/6 code rate using Xilinx XPower tool. In this paper, we propose two novel techniques, sub-matrix reordering and differential shifting, for reducing the power consumption of a LDPC decoder hardware. We applied glitch reduction, sub-matrix reordering and differential shifting techniques to our LDPC decoder hardware. These techniques do not affect the bit error rate (BER) of a LDPC decoder. For block length 648 and code rate 1/2, these three techniques together reduced the power consumption of the LDPC decoder hardware in total by 23.7% to 1,565.84 mW. For block length 648 and code rate 5/6, they together reduced the power consumption of the LDPC decoder hardware in total by 38.98% to 1,214.22 mW.