Digital design of serial flash memory controller with SPI interface for embedded systems

Official URL: http://risc01.sabanciuniv.edu/record=b1121741 (Table of Contents)

This thesis presents digital design and implementation of a controller module for serial flash memories. Firstly, the platform including the serial flash memory controller, flash memories and SPI (Serial Peripheral Interface) protocol have been investigated to solve the current problems related with controlling of serial flash memories. Then, in the implementation part of the thesis, the Serial Flash Memory Controller module has been designed by using VHDL (VHSIC Hardware Description Language-VHDL) and synthesized in CMOS 0.35 Mm technology. Functional and gate-level simulations have been done with Cadence simulator. Lastly the final gate level netlist has been placed and routed with Cadence Silicon Ensemble. A great deal of attention has been given to design a generic controller that needs simple software and minimum processor access cycle. It is programmed from the processor for different operations of serial flash memories. The structure of the frame, control data and timings are controlled by hardware according to the programmed operation. In addition to this, our Serial Flash Memory Controller module can be used with different flash memories. This is very important property for reusability of the module. The Serial Flash Memory Controller module is capable to work up to 20 MHz serial communication speed and it can be integrated to processor platforms that have AMBA (Advanced Microcontroller Bus Architecture) APB (Advanced Peripheral Bus) interface.