Digital implementation of ETSI OFDM symbol synchronizer based on sliding correlation

Official URL: http://risc01.sabanciuniv.edu/record=b1080576 (Table of Contents)

This thesis presents the design, implementation, verification and synthesis of a digital hardware, which performs OFDM symbol synchronization using short training symbols (STS) defined in European Telecommunications Standards Institute (ETSI) HiperLan/2 Physical Layer specifications. Designed ETSI OFDM Symbol Synchronizer IP was synthesized in CMOS 0.13mM technology using Virtual Silicon Technology (VST) Standard Cell Libraries. In this thesis, we first explain OFDM and OFDM systems in detail. Synchronization problems occurring in OFDM systems are classified and techniques used to overcome these problems are presented. Then a digital ETSI OFDM Symbol Synchronizer IP, which performs OFDM symbol synchronization task based on the correlation of the received symbols, is proposed. Proposed architecture has been designed using VHDL (VHSIC Hardware Description Language) in the implementation part of the thesis. Designed IP has been verified functionally first, then synthesized in CMOS 0.13mM technology. Gate-level verification has been also performed after synthesis of the IP. Like other communication systems, synchronization is a critical problem to be solved in OFDM systems. One of the arguments against OFDM is that it is highly sensitive to synchronization errors. Before an OFDM receiver can demodulate the subcarriers, it has to perform at least two synchronization tasks: First, it has to find out where the symbol boundaries are. Second, it has to estimate and correct the carrier frequency offset of the received signal and clock offset between transmitter and receiver because any offset introduces Inter-carrier interference (ICI) and Inter-symbol interference (ISI). This work aims to review OFDM and synchronization issues in OFDM systems and to design a digital symbol synchronizer hardware that performs the detection of OFDM symbols, which is the first synchronization task mentioned above. ETSI HiperLAN/2 standard has been used in this work as the reference for all parameters needed and used in the hardware implementation of ETSI OFDM Symbol Synchronizer. Although the needed sampling frequency of OFDM receiver is 20 MHz in the ETSI standards, the designed IP can be run up to 50 MHz. It can be easily adapted to any changes in the standard, such as the increase in speed. The generically designed ETSI OFDM STS Symbol Synchronizer IP can be integrated to other modules easily and used as part of the whole synchronizer block in ETSI OFDM receivers.