An investigation into bandwith expansion and signal integrity of frequency-multiplier-last transmitters

The evolution of wireless communications necessitates transmitters capable of achieving data rates in the range of tens of gigabits per second. Due to high congestion and strict regulations, lower-frequency bands are unlikely to satisfy the growing data-rate demands set by regulatory bodies such as the International Telecommunication Union (ITU). Consequently, sub-THz frequencies (above 100 GHz) are being explored as viable alternatives for high-speed wireless communication.However, the relatively low maximum operating frequencies of CMOS transistors pose limitations for conventional transmitter architectures, which typically rely on power amplifiers in their final stage. To address this challenge, frequency-multiplier-last transmitters have been proposed, enabling efficient frequency upconversion to sub-THz bands using solely CMOS technology. Despite their advantages, these transmitters introduce significant distortions due to the frequency multiplier stage, negatively impacting digital communication performance.This thesis presents a mathematical system-level analysis of these impairments. The analysis demonstrates that even-order multipliers are inadequate for supporting digital IQ modulation-based communication between the transmitter and receiver. It further reveals that the signal-to-noise ratio (SNR) degrades proportionally to the square of the multiplier order. The thesis concludes that the frequency tripler is the most suitable option for digital communication in frequency-multiplier-last transmitters.