FPGA implementation of deep neural networks (dnns)For fast inference and error resilience analysis

Deep learning, a subset of machine learning, has revolutionized numerous fields by itsability to model complex patterns and make highly accurate predictions. As Deep NeuralNetworks (DNNs) are increasingly deployed in critical applications, ensuring their reliabilityand robustness becomes paramount. Error resilience refers to a network’s abilityto maintain acceptable performance despite encountering faults or errors. These errorscan stem from various sources, including hardware defects, environmental conditions,and operational stresses. Deploying DNNs on edge devices, such as mobile phones, IoT(Internet of Things), and embedded systems, presents unique challenges due to limitedcomputational power, memory, and energy availability. Exploiting the error resilience ofDNNs can significantly enhance energy efficiency for edge devices.This thesis introduces an error injection framework aimed at evaluating the resilience ofconvolutional neural networks (CNNs) to bit-level faults. This framework employs a 2Derror matrix format to achieve error injection at both the per-bit and per-layer levels.The dimensions of the matrix align with the number of error injection layers (rows) andthe quantization bit width (columns). Each element in the matrix represents the biterror rate for a specific layer and bit position, allowing for precise and detailed errorsimulation.Real-time error injection simulations, where faults are introduced dynamically duringthe network’s operation, add another layer of computational demand. These simulationsmust accurately emulate real-time conditions and network responses, often requiring highfrequencyprocessing and low-latency computation.To efficiently implement this advanced framework, it was deployed on the AMD XilinxUltrascale+ SoC using the Vitis AI platform. The framework was further enhanced by designing a specialized Error Injection IP in Verilog HDL. This IP facilitates the injectionof errors into the outputs of convolutional and fully connected layers. The Error InjectionIP performs error injection using an XOR gate based on the generated bit errors.The Error Injection IP includes a Linear Feedback Shift Register (LFSR) to generaterandom errors, and the filter module is designed to ensure efficient and controlled fault injection.