An 8-bit 100 ms/s time-interleaved sar-assisted pipeline adc with improved residue amplifier

Ninan Kunnatharayil, Cerin (2022) An 8-bit 100 ms/s time-interleaved sar-assisted pipeline adc with improved residue amplifier. [Thesis]

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Abstract

In a successive approximation register (SAR)-assisted pipeline analog-to-digital converters (ADC), SAR ADC and residue amplifier are the two blocks that determine the speed and power of the ADC. Among them, the residue amplifier is the most power-hungry. Traditionally, the residue amplifier uses a high-gain op-amp, but as the CMOS technology scales, the intrinsic gain of the transistor reduces. Hence, the residue amplifier is designed based on zero-crossing-based circuits (ZCBCs) as it is not affected by the scaling down of the CMOS technology. The limitation of the ZCBC-based residue amplifier is the overshoot voltage arising for technology nodes that have low fT. Hence, a novel overshoot reduction technique is introduced in the residue amplifier. The overshoot voltage and time were simulated for different corner cases. The final range of the overshoot voltage and time after implementing the novel overshoot reduction technique was attained from 0.584 mV to 1.59 mV and 124 ps to 423 ps, respectively. The percentage reduction in the overshoot time and voltage ranges w.r.t to the case when the overshoot reduction technique was not used ranges from 90.544 % to 98.012 % and 89.153 % to 97.67 %, respectively. The novel overshoot reduction technique was implemented in the 2-bit/cycle sub-radix Vcm-based SAR-assisted pipeline ADC. The post-layout simulation results show an SNDR, an SFDR, and an ENOB of 56.57 dB, 62.98 dB, and 9.1046 bits, respectively with a sampling speed of 25 MHz at a near Nyquist frequency of 11.328125 MHz, and the ADC consumes a power of 8.212 mW. The 2-bit/cycle sub-radix Vcm-based SAR-assisted pipeline ADC was implemented in a 4-channel Time-Interleaved ADC. The post-layout SNDR, SFDR, and ENOB were attained as 50.04 dB, 54.78 dB, and 8.0198 bits, respectively with a sampling speed of 100 MHz at a near Nyquist frequency of 44.140625 MHz.
Item Type: Thesis
Uncontrolled Keywords: High-speed SAR logic. -- Residue Amplifier. -- SAR-Assisted Pipeline ADC. -- Simultaneous-Switching Noise (SSN). -- Zero-Crossing Detector (ZCD). -- Yüksek hızlı SAR mantığı. -- Artık Yükseltici. -- SAR Destekli Boru Hattı ADC. -- Eşzamanlı Anahtarlama Gürültüsü (SSN). -- Sıfır Geçiş Dedektörü (ZCD).
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: Dila Günay
Date Deposited: 24 Apr 2023 10:19
Last Modified: 24 Apr 2023 10:19
URI: https://research.sabanciuniv.edu/id/eprint/47039

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