An overshoot voltage reduction technique with improved speed for zero-crossing detector in pipeline ADCs

Official URL: https://dx.doi.org/10.1109/ISCAS48785.2022.9937960

A two-step approach is introduced to reduce the overshoot voltage and increase the speed of the zero-crossing detector (ZCD) in a SAR-assisted pipeline ADC. The technique detects the zero-crossing of the input without reducing the speed of the current source and thereby, achieves a minimum overshoot voltage with improved speed. The proposed technique achieves a maximum of 2.8 mV of overshoot voltage with an amplification time of 1.34 ns. The proposed technique is implemented in an 8b radix-1.8 \mathrm{V}-{\mathrm{cm}}-based SAR-assisted two-stage pipeline ADC in 130 nm SiGe BiCMOS technology. The post-layout simulation results achieve an ENOB of 7.3965 bits and 6.7667 bits that corresponds to an SNDR of 46.287 dB and 42.287 dB with a sampling rate of 20 MS/s at an input frequency of 1.3021 MHz and at the Nyquist frequency, respectively.