Hamzaoğlu, İlker and Mahdavi, Hossein and Taşkın, Elif (2022) FPGA implementations of VVC fractional interpolation using high-level synthesis. In: IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA
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Official URL: https://dx.doi.org/10.1109/ICCE53296.2022.9730363
Abstract
In this paper, the first FPGA implementations of Versatile Video Coding (VVC) fractional interpolation algorithm using a high-level synthesis (HLS) tool in the literature are proposed. Three different C++ codes are developed. They implement constant multiplications with multiplication operations, addition and shift operations, and multiplierless constant multiplication algorithm, respectively. These C++ codes are synthesized using Xilinx Vivado HLS tool. The best proposed HLS implementation can process 62 full HD (1920×1080) video frames per second. It has higher performance than manual VVC fractional interpolation hardware implementations at the cost of larger area.
| Item Type: | Papers in Conference Proceedings |
|---|---|
| Uncontrolled Keywords: | FPGA; Fractional Interpolation; HLS; VVC |
| Divisions: | Faculty of Engineering and Natural Sciences > Academic programs > Electronics Faculty of Engineering and Natural Sciences |
| Depositing User: | İlker Hamzaoğlu |
| Date Deposited: | 23 Aug 2022 15:12 |
| Last Modified: | 23 Aug 2022 15:35 |
| URI: | https://research.sabanciuniv.edu/id/eprint/44093 |
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