An efficient approximate sum of absolute differences hardware for FPGAs

Official URL: https://dx.doi.org/10.1109/ICCE50685.2021.9427756

In this paper, we propose an efficient approximate sum of absolute differences (SAD) hardware with very small maximum and average error for FPGAs. The proposed approximate SAD hardware utilizes the unused LUT inputs to reduce area and power consumption while providing an almost accurate result. The proposed approximate SAD hardware has smaller maximum and average error than the approximate SAD hardware in the literature. It uses up to 20% less LUTs than the smallest approximate SAD hardware in the literature. It consumes up to 38% less power than the lowest power consuming approximate SAD hardware in the literature.