A 32-Gb/s PAM-4 SST transmitter with four-tap FFE using high-impedance driver in 28-nm FDSOI

Official URL: https://dx.doi.org/10.1109/TVLSI.2021.3068242

With increasing modulation order, a larger number of parallel source-series-terminated (SST) segments are required to implement precise feedforward equalization (FFE) tap-weight control in SST transmitters (TX). Due to the data routing complexity of the segmented structure, the dynamic power consumption of SST TX has become much more significant causing degradation in energy efficiency. This article presents a 32-Gb/s quarter-rate four-level pulse-amplitude modulation (PAM-4) SST TX with four-tap FFE implemented in 28-nm FDSOI CMOS technology using a high-impedance driver technique to decrease the gate loading of the data path of the SST TX. The output of the whole TX is kept matched to the standard characteristic impedance of the system even though the output impedance of the SST driver alone is high. The high-impedance driver technique decreases the total power consumption by 20% compared to the conventional design by providing a significant reduction in the capacitive load. Our measurement results show that the prototype TX consumes 77.9 mW and achieves an energy efficiency of 2.4 pJ/bit at a 32-Gb/s data rate for PAM-4 signaling.