Process integration and technology development for low-cost, accessible high density interconnect (HDI) printed circuit boards (PCBS)

Official URL: https://risc01.sabanciuniv.edu/record=b2708517_(Table of contents)

With the growing demand towards 5G and beyond mobile communications, multilayer printed circuit boards utilizing microvias and populated network of electrical wiring to enable highly dense three-dimensional circuit assemblies; otherwise known as highdensity interconnect printed circuit boards (HDI-PCB), are becoming a critical enabler for next generation electronic equipment. Although the fundamental difference between HDI-PCBs and traditional PCBs is essentially in the density of electrical interconnects, such difference calls for a paradigm shift in the printed circuit board architecture requiring multilayer stack-up with laser-drilled microvias, buried and blind vias for layer-to-layer electrical interfacing as well as linewidths with resolutions far below typical PCBs. All in all, HDI-PCBs require new fabrication strategies, optimized unit processes (e.g. lithograpy, etching, via drilling and plating) and integration thereof with stringent process control to achieve the specifications set-forth by different HDI-PCB classifications, which understandably comes at a cost and requires special infrastructure. The intention of this thesis is therefore to provide an accessible and low-cost process flow to realize HDI-PCBs by leveraging the capabilities of mechanical drilling to their extent along with basic lab equipment to achieve Type-III-based, 2-N-2 HDI-PCB architecture. A detailed and optimized fabrication flow is developed in order to establish a reliable and repeatable process flow starting from stacking of the “base” materials (prepreg/core/Cu laminates) up to the final solder mask level. In the developed HDI-PCB process technology, each unit process is experimentally verified and optimized, after which all the unit processes are sequentially performed to achieve an integrated process flow. Specifically, the developed and optimized unit processes include: prepreg/copper lamination, mechanical microvia (100 µm) drilling, microvia metallization (electroless and electroplating of copper, reverse-etch of overfilled vias), high-density fine line lithography and low-undercut etching. Accordingly, based on the developed process technology, prepreg/Cu lamination was achieved with a 5.93% height difference for sequential build-up architecture. Drilling of 100 µm vias in 175 µm via pads with center-to-center spacing of 250 µm was achieved within a 10% error margin throughout 10×10 cm active HDI board area. Dry and liquid photoresists systems for patterning of copper layers with 50 µm line width and 50 µm line gap is achieved on 18 µm copper foils. Electroless copper plating for the metallization of holes and selective copper electroplating for via filling process flow is developed and realized. Dry film solder mask (75 µm) application was achieved by streo-microscope assisted manual alignment and UV-box flood exposure system, overcoming the limits of typical mask aligner system for thick materials requiring large depth-of-focus microscopes for alignment.