Low energy motion estimation hardware designs for h.264 multiview video coding

Official URL: http://risc01.sabanciuniv.edu/record=b1615032 (Table of Contents)

Multiview Video Coding (MVC) is the process of efficiently compressing stereo (2 views) or multiview video signals. The improved compression efficiency achieved by H.264 MVC comes with a significant increase in computational complexity. Temporal prediction and inter-view prediction are the most computationally intensive parts of H.264 MVC. Therefore, in this thesis, we propose an H.264 MVC full search motion estimation hardware for implementing the temporal and inter-view predictions including several novel energy reduction techniques. The proposed motion estimation hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 60 frames per second of VGA size stereo view video sequence. It consumes 65% less energy than H.264 MVC full search motion estimation hardware not including the novel energy reduction techniques with very small PSNR loss and bitrate increase. We also propose a vector prediction based fast motion estimation algorithm for reducing the energy consumption of H.264 MVC motion estimation hardware with additional very small PSNR loss and bitrate increase. We also propose an H.264 MVC motion estimation hardware for implementing the proposed fast motion estimation algorithm. The proposed motion estimation hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 92 frames per second of VGA size three view video sequence. It consumes 91% less energy than H.264 MVC full search motion estimation hardware not including the novel energy reduction techniques with very small PSNR loss and bitrate increase.