Dynamic power reduction in digital pixel design for large format focal plane arrays

Official URL: http://dx.doi.org/10.1016/j.mejo.2016.10.003

This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90 nm CMOS process with pixel pitch of 30 µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28 mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256×256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise.