A low energy HEVC inverse transform hardware

Official URL: http://dx.doi.org/10.1109/TCE.2014.7027352

In this paper, a novel energy reduction technique for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) and Inverse Discrete Sine Transform (IDST) for all transform unit (TU) sizes is proposed. The proposed technique calculates IDCT and IDST only for DC coefficient if the values of several predetermined forward transformed low frequency coefficients in a TU are smaller than a threshold. The proposed technique reduces the computational complexity of IDCT and IDST significantly. It increases the bit rate slightly for most video frames. It decreases the PSNR slightly for some video frames, and it increases the PSNR slightly for some video frames. In this paper, a low energy HEVC 2D inverse transform (IDCT and IDST) hardware for all TU sizes is also designed and implemented using Verilog HDL. In the worst case, the proposed hardware can process 48 Quad HD (3840x2160) video frames per second. The proposed technique reduced the energy consumption of this hardware up to 32%. Therefore, the proposed hardware can be used in portable consumer electronics products that require a real-time HEVC encoder.(1)