A high performance and low energy hardware for intra prediction with template matching

Official URL: http://dx.doi.org/10.1109/VLSI-SoC.2013.6673290

H.264 intra prediction algorithm is not well suited for processing complex textures at low bit rates. Therefore, intra prediction with Template Matching (TM) is proposed for improving H.264 intra prediction. However, intra prediction with TM has high computational complexity. Therefore, in this paper, we propose a novel technique for reducing the amount of computations performed by intra prediction with TM, and therefore reducing the energy consumption of intra prediction with TM hardware. The proposed technique does not change the PSNR for some video frames, but it decreases the PSNR slightly for some video frames. We also designed and implemented a high performance 4×4 intra prediction with TM hardware including the proposed technique using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The FPGA implementation is capable of processing 53 HD (1280×720) frames per second, and the proposed technique reduced its energy consumption up to 50%.