A high performance deblocking filter hardware for high efficiency video coding

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Özcan, Erdem and Adıbelli, Yusuf and Hamzaoğlu, İlker (2013) A high performance deblocking filter hardware for high efficiency video coding. In: 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto

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Abstract

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. In this paper, we propose the first HEVC deblocking filter hardware in the literature. Two parallel datapaths are used in the hardware to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work at 108 MHz in a Xilinx Virtex 6 FPGA. The proposed HEVC deblocking filter hardware can code 30 full HD (1920×1080) video frames per second. It can be used in an HEVC encoder or an HEVC decoder.
Item Type: Papers in Conference Proceedings
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: İlker Hamzaoğlu
Date Deposited: 14 Jan 2014 11:54
Last Modified: 26 Apr 2022 09:13
URI: https://research.sabanciuniv.edu/id/eprint/23453

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