A high performance deblocking filter hardware for high efficiency video coding

Official URL: http://dx.doi.org/10.1109/FPL.2013.6645602

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. In this paper, we propose the first HEVC deblocking filter hardware in the literature. Two parallel datapaths are used in the hardware to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work at 108 MHz in a Xilinx Virtex 6 FPGA. The proposed HEVC deblocking filter hardware can code 30 full HD (1920×1080) video frames per second. It can be used in an HEVC encoder or an HEVC decoder.