Sub-pixel accurate h.264 motion estimation hardware design

Öktem, Serkan Hikmet (2007) Sub-pixel accurate h.264 motion estimation hardware design. [Thesis]

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The new international standard for video compression named H.264 / MPEG-4 Part 10 offers significantly better video compression efficiency than previous international standards. Integer-pixel motion estimation is the most compute-intensive part of an H.264 video encoder. In order to increase the performance of integer-pixel motion estimation, sub-pixel (half-pixel and quarter-pixel) accurate variable block size motion estimation is performed. In this thesis, we developped an efficient hardware architecture for real-time implementation of sub-pixel accurate variable block size ME for H.264 video coding standard. We have considered several alternative designs and decided on this architecture based on a cost/performance analysis. The proposed hardware includes novel half-pixel and quarter-pixel interpolation and search hardwares designed for each block size. In the proposed hardware, half-pixel interpolation hardwares are shared by half-pixel search hardwares for reducing area. The proposed design performs quarter-pixel interpolation dynamically for reducing the amount of computation performed for quarter-pixel interpolation and therefore reducing the power consumption. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed hardware architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 60 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 34 VGA frames (640x480) per second.
Item Type: Thesis
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: IC-Cataloging
Date Deposited: 28 Jul 2010 12:50
Last Modified: 26 Apr 2022 09:52

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