High performance hardware architecture for half-pixel accurate H.264 motion estimation

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Yalçın, Sinan and Hamzaoğlu, İlker (2006) High performance hardware architecture for half-pixel accurate H.264 motion estimation. In: IFIP International Conference on VLSI-SoC, Nice

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Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of half-pel accurate variable block size motion estimation for H.264 / MPEG4 Part 10 video coding. The proposed architecture includes a novel half-pel interpolation hardware that is shared by novel half-pel search hardwares designed for each block size. This half-pel accurate motion estimation hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 85 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 30 HDTV frames (1280x720) per second.
Item Type: Papers in Conference Proceedings
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Natural Sciences
Depositing User: İlker Hamzaoğlu
Date Deposited: 17 Dec 2006 02:00
Last Modified: 26 Apr 2022 08:33
URI: https://research.sabanciuniv.edu/id/eprint/1237

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