H.264 Intra frame coder system design /

Taşdizen, Özgür (2005) H.264 Intra frame coder system design /. [Thesis]

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Recently, a new international standard for video compression named H.264 / MPEG4 Part 10 is developed. This new standard offers significantly better video compression efficiency than previous International standards. However, this coding gain comes with an increase in encoding complexity. This makes it impossible to implement a real time H.264 video coder using the state-of-the-art embedded processor alone. Therefore, in this thesis, we developed an FPGA-based H.264 intra frame coder system for portable applications targeting level 2.0 of baseline profile. As part of the system, we first designe a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard in Verilog HDL. The design is first veryfied with RTL simulations using Mentor Graphics Modelism. It is then verified to work on a Xilinx Virtex II FPGA on an ARM Versatile Platform development board. We then designed the top-level H.264 Intra Frame Coder System targeting 30 fps CIF encoding. The system consists of search, mode decision and coding parts. The mode decision part implements a Hadamard Transform based mode decision algorithm. The coding part is implemented by integrating Transform-Quant module with CAVLC and Intra Prediction modules. The top-level design is verified with RTL simulations using Menthor Graphics Modelism. The complete H.264 Intra Frame Coder System is verified to work on an ARM Versatile Platform development board. The verification includes first capturing an RGB image, converting it into YCbCr format, partitioning the image into macroblocks, and writing it into a SRAM using the software running on ARM9EJ-S processor. Then the intra frame coder hardware mapped to the Xilinx Virtex II FPGA using Leonardo Spectrum and Xilinx ISE is used to encode the image and reconstruct it. The conversion of reconstucted image into raster scan order and RGB color domain is then performed by software running on ARM9EJ-S processor. The reconsructed image is then displayed on acolor LCD panel for visual verification.
Item Type: Thesis
Uncontrolled Keywords: FPGA -- Video compression -- VLSI -- HDL
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: IC-Cataloging
Date Deposited: 15 Apr 2008 14:03
Last Modified: 26 Apr 2022 09:45
URI: https://research.sabanciuniv.edu/id/eprint/8282

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