A low-latency reconstruction-based symbol error correction for PAM-4 DSP-based wireline receivers

Official URL: https://dx.doi.org/10.1109/TCSI.2026.3722199

This paper proposes a decision-error correction scheme that improves the pre-forward error correction (pre-FEC) bit-error rate (BER) by identifying and correcting symbol errors after the decision feedback equalizer (DFE) without introducing any coding overhead. The proposed method reconstructs the received waveform to localize error-prone symbols without requiring additional redundancy and performs symbol-level correction by exploiting intrinsic properties of pulse-amplitude modulation (PAM) signaling. The error detection and correction scheme is implemented using simple digital arithmetic and logic and completes the correction process within three digital signal processor (DSP) clock cycles, thereby avoiding excessive latency. A 4-level pulse-amplitude modulation (PAM-4) DSP employing a 64-way parallel datapath was implemented in a 14-nm FinFET process, occupying 0.269 mm2 and targeting an 875 MHz clock frequency. The design was validated on a Xilinx ZCU111 RFSoC platform, demonstrating a BER improvement of more than five orders of magnitude at 4.8 Gb/s over a channel with 22.9 dB insertion loss (IL) at Nyquist.