Hirlak, Kenan Cagri and Niar, Smail and Öztürk, Özcan (2026) OpenCL-based deeply pipelined HLS implementation for iterative graph applications. In: 36th Great Lakes Symposium on VLSI, GLSVLSI 2026, Canandaigua, NY, USA
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Official URL: https://dx.doi.org/10.1145/3787109.3815260
Abstract
Graph applications play a central role in different domains such as machine learning, data analytics, natural language processing, and fraud detection. Generating highĝ€'performance kernels tailored to custom accelerator architectures for such workloads remains challenging due to their irregular memory access patterns and dataĝ€'dependent control flow. We propose an OpenCLĝ€'based framework for the automated generation of deeply pipelined High Level Synthesis (HLS) implementations of iterative graph algorithms. The framework integrates a set of optimization techniques that restructure iterative graph algorithms to maximize pipeline utilization, reduce memory bottlenecks, and enable aggressive HLS optimizations. Although broadly applicable to a wide class of iterative graph workloads, we demonstrate the approach using PageRank as a representative case study. The experiment results demonstrate that efficient synthesis and high throughput can be obtained. The generated deeply pipelined HLS kernels can deliver substantial performance benefits for graphĝ€'centric FPGA acceleration.
| Item Type: | Papers in Conference Proceedings |
|---|---|
| Uncontrolled Keywords: | Breadth First Search (BFS); Connected Components; Field Programmable Gate Array (FPGA); Graph Algorithms; High-Level Synthesis (HLS); Machine Learning; OpenCL; PageRank (PR) |
| Divisions: | Faculty of Engineering and Natural Sciences |
| Depositing User: | Özcan Öztürk |
| Date Deposited: | 28 Aug 2026 10:36 |
| Last Modified: | 28 Aug 2026 10:36 |
| URI: | https://research.sabanciuniv.edu/id/eprint/54342 |

