Fast and accurate SystemVerilog framework for mixed-signal modeling of PAM-4 wireline transceivers

Official URL: https://dx.doi.org/10.1109/ISCAS66217.2026.11562858

This paper presents a SystemVerilog-based modeling and simulation methodology for a 4-level pulse-amplitude-modulation (PAM-4) transceiver. The framework is developed to address verification challenges in complex analog-to-digital converter (ADC)-based mixed-signal systems, where conventional circuit-level simulations suffer from prohibitively long execution time. Two key modeling techniques to significantly improve simulation efficiency are introduced in this work. For the time-interleaved ADC (TI-ADC), a counter-based equivalent circuit model is employed to capture dominant rank-1 mismatch errors while substantially reducing modeling complexity. In addition, for digital clock and data recovery (CDR), a statistical bit-error-rate (BER) evaluation approach based on XMODEL primitives is adopted as an alternative to conventional time-domain analog-mixed-signal (AMS) simulations. This modeling framework enables accurate verification of critical transceiver performance metrics, such as jitter tolerance (JTOL), within a 30-minute simulation window. Compared to conventional timedomain simulations, which require more than 12 hours to perform, the proposed approach achieves approximately a 24× improvement in simulation speed.