Modeling and simulation of Mueller-Muller clock data recovery system for PAM-4 wireline transceivers

Official URL: https://dx.doi.org/10.1109/ICCE-Asia67487.2025.11263607

In high-speed links, limited channel bandwidth and frequency-dependent loss increase inter-symbol interference (ISI). Moreover, imperfect synchronization between the transmitter (TX) and receiver (RX) clocks introduces timing offset and jitter, which further degrade sampling accuracy. This paper presents a model of a Mueller-Muller phase detector (MMPD)based clock and data recovery (CDR) system and investigates its performance. For efficient analysis, XMODEL, a high-speed link simulation tool, is used to achieve runtime reduction compared to conventional simulators, enabling efficient evaluation of very low bit error rates (BER). A complete transmitter-receiver (TRX) architecture is constructed under channel loss conditions, with an analog-to-digital converter (ADC)-based receiver architecture employing a phase interpolator (PI)-based Mueller-Muller clock and data recovery (MMCDR) system. Two phase detector structures are modeled for comparative analysis: sign-sign MMPD (SS-MMPD) and linear MMPD.