LNA designs for 5G receiver applications

Official URL: https://dx.doi.org/10.1109/APMC52720.2021.9661791

This brief presents two low-power, low-noise amplifiers (LNAs) centered at 28 GHz for 5G receiver applications. Both LNAs are realized in a 0.13-μm SiGe BiCMOS technology and are based on a single-stage cascode topology. While in the first version, the conventional cascode design is followed, a noise reduction technique is applied in the second version. In this technique, a shunt inductance to the intermediate node of the topology is added to reduce the noise contribution of the common-base transistor of the LNA. The drawback of the proposed noise reduction method is a small gain drop. The fabricated LNAs achieve state-of-the-art performances at 28 GHz with an input-referred 1-dB compression point (IP1dB) of -10.5 dBm, a noise figure of 2.26 dB and 2.08 dB, and a gain of 14.5 dB and 12.8 dB, respectively while consuming 5.4 mW DC power. The realized LNAs occupy a 0.23 mm2, for the conventional one, and 0.3 mm2, for the proposed one, with pads.