FPGA implementation of HEVC intra prediction using high-level synthesis

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Kalalı, Ercan and Hamzaoğlu, İlker (2016) FPGA implementation of HEVC intra prediction using high-level synthesis. In: IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin 2016), Berlin, Germany

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Abstract

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is proposed. The proposed HEVC intra prediction hardware, in the worst case, can process 35 full HD (1920×1080) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.
Item Type: Papers in Conference Proceedings
Uncontrolled Keywords: FPGA, HEVC, Intra Prediction, HLS
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: İlker Hamzaoğlu
Date Deposited: 08 Nov 2016 12:23
Last Modified: 26 Apr 2022 09:25
URI: https://research.sabanciuniv.edu/id/eprint/30681

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