A reconfigurable HEVC sub-pixel interpolation hardware

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Kalalı, Ercan and Adıbelli, Yusuf and Hamzaoğlu, İlker (2013) A reconfigurable HEVC sub-pixel interpolation hardware. In: IEEE Third International Conference on Consumer Electronics Berlin (ICCEBerlin 2013), IFA Fairground, Berlin, Germany

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Abstract

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. Therefore, in this paper, a reconfigurable HEVC sub-pixel (half-pixel and quarter-pixel) interpolation hardware for all prediction unit sizes is proposed. The proposed reconfigurability reduces the area and power consumption of HEVC sub-pixel interpolation hardware more than 30%. The proposed hardware, in the worst case, can process 64 quad full HD (2560×1600) video frames per second.
Item Type: Papers in Conference Proceedings
Uncontrolled Keywords: HEVC, Sub-pixel Interpolation, Hardware Implementation, FPGA
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: İlker Hamzaoğlu
Date Deposited: 14 Jan 2014 10:34
Last Modified: 26 Apr 2022 09:13
URI: https://research.sabanciuniv.edu/id/eprint/23455

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