A high performance hardware architecture for one bit transform based motion estimation

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Akın, Abdulkadir and Doğan, Yiğit and Hamzaoğlu, İlker (2009) A high performance hardware architecture for one bit transform based motion estimation. In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Patras, Greece

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Abstract

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (IBT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose a high performance systolic hardware architecture for IBT based ME. The proposed hardware performs full search ME for 4 Macroblocks in parallel and it is the fastest IBT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous IBT based ME hardware by using a novel data reuse scheme and memory organization. The proposed hardware is implemented in Verilog HDL. It consumes %34 of the slices in a Xilinx XC2VP30-7 FPGA. It works at 115 MHz in the same FPGA and is capable of processing 50 1920x1080 full High Definition frames per second. Therefore, it can be used in consumer electronics products that require real-time video processing or compression.
Item Type: Papers in Conference Proceedings
Uncontrolled Keywords: Motion Estimation, One-Bit Transform, Hardware Implementation, FPGA
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Faculty of Engineering and Natural Sciences
Depositing User: İlker Hamzaoğlu
Date Deposited: 02 Nov 2009 17:20
Last Modified: 26 Apr 2022 08:51
URI: https://research.sabanciuniv.edu/id/eprint/12417

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