An efficient hardware architecture for quarter-pixel accurate H.264 motion estimation

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Öktem, Serkan Hikmet and Hamzaoğlu, İlker (2007) An efficient hardware architecture for quarter-pixel accurate H.264 motion estimation. In: 10th Euromicro Conference on Digital System Design, Lübeck, Germany

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Abstract

In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10 video coding. The proposed hardware performs quarter-pixel interpolation dynamically, i.e. only the quarter pixels necessary for performing quarter-pixel accurate search at the location pointed by the half-pixel motion vector are calculated. This reduces the amount of computation performed for quarter-pixel interpolation, and therefore reduces the power consumption of the quarter-pixel accurate motion estimation hardware. This hardware is designed to be used as part of a complete H. 264 video coding system for portable applications. The proposed hardware architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 60 MHz in a Xilinx Virtex IIFPGA. The FPGA implementation can process 34 VGA frames (640x480) per second.
Item Type: Papers in Conference Proceedings
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
Divisions: Faculty of Engineering and Natural Sciences > Academic programs > Electronics
Depositing User: İlker Hamzaoğlu
Date Deposited: 15 Nov 2008 14:43
Last Modified: 26 Apr 2022 08:49
URI: https://research.sabanciuniv.edu/id/eprint/10732

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