An efficient H.264 intra frame coder system design

Official URL: http://dx.doi.org/10.1109/VLSISOC.2007.4402498

In this paper, we present an efficient H.264 / MPEG4 Part 10 Intra Frame Coder System. The system achieves real-time performance for portable applications with low hardware cost, and it includes a novel intra prediction hardware design. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code works at 71 MHz in a Xilinx Virtex II FPGA and it code 35 CIF frames (352×288) per second. The system also includes a software running on an Arm926EJS processor for implementing pre-processing and post-processing functions. The H.264 Intra Frame Coder hardware and software are demonstrated to work together on an Arm Versatile Platform development board.