High performance HEVC and FVC video compression hardware designs
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Mert, Ahmet Can (2017) High performance HEVC and FVC video compression hardware designs. [Thesis]
Official URL: http://risc01.sabanciuniv.edu/record=b1659262 (Table of Contents)
High Efficiency Video Coding (HEVC) is the current state-of-the-art video compression standard developed by Joint collaborative team on video coding (JCT-VC). HEVC has 50% better compression efficiency than H.264 which is the previous video compression standard. HEVC achieves this video compression efficiency by significantly increasing the computational complexity. Therefore, in this thesis, we proposed a low complexity HEVC sub-pixel motion estimation (SPME) technique for SPME in HEVC encoder. We designed and implemented a high performance HEVC SPME hardware implementing the proposed technique. We also designed and implemented an HEVC fractional interpolation hardware using memory based constant multiplication technique for both HEVC encoder and decoder. Future Video Coding (FVC) is a new international video compression standard which is currently being developed by JCT-VC. FVC offers much better compression efficiency than the state-of-the-art HEVC video compression standard at the expense of much higher computational complexity. In this thesis, we designed and implemented three different high performance FVC 2D transform hardware. The proposed hardware is verified to work correctly on an FPGA board.
|Additional Information:||Yükseköğretim Kurulu Tez Merkezi Tez No: 478650.|
|Uncontrolled Keywords:||HEVC. -- Sub-Pixel motion estimation. -- Fractional İnterpolation. -- FVC. -- 2D Transform. -- HEVC. -- Ara piksel hassaslığında hareket tahmini. -- Ara piksel hesaplama. -- FVC. -- 2B Dönüşüm.|
|Subjects:||T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics |
|Deposited On:||09 May 2018 09:54|
|Last Modified:||25 Mar 2019 17:27|
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