FPGA implementations of HEVC sub-pixel interpolation using high-level synthesis

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Abdul Ghani, Firas and Kalalı, Ercan and Hamzaoğlu, İlker (2016) FPGA implementations of HEVC sub-pixel interpolation using high-level synthesis. In: International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS 2016), Istanbul, Turkey

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Official URL: http://dx.doi.org/10.1109/DTIS.2016.7483883


Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC sub-pixel (half-pixel and quarter-pixel) interpolation algorithm using a HLS tool in the literature is proposed. The proposed HEVC sub-pixel interpolation hardware is implemented on Xilinx FPGAs using Xilinx Vivado HLS tool. It, in the worst case, can process 45 quad full HD (3840×2160) video frames per second. Using HLS tool significantly reduced the FPGA development time. Therefore, HLS tools can be used for FPGA implementation of HEVC video encoder.

Item Type:Papers in Conference Proceedings
Uncontrolled Keywords:FPGA, HEVC, Sub-Pixel Interpolation, HLS
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
ID Code:30674
Deposited By:İlker Hamzaoğlu
Deposited On:14 Nov 2016 11:24
Last Modified:14 Nov 2016 11:24

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