A new digital readout integrated circuit (DROIC) with pixel parallel A/D conversion with reduced quantization noise

Official URL: http://dx.doi.org/10.1117/12.2054640

This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge(-) with quantization noise higher than 1000e(-). Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 161 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge(-). A prototype array of 32x32 pixels with 30um pitch is implemented in 90nm CMOS process technology for verification. Measurement results are given for complete readout.