Post processing for checking sequences

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Cirit, Semen (2011) Post processing for checking sequences. [Thesis]

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There are several methods to generate a checking sequence (CS) from a given Finite State Machine M. These methods generate a CS in such a way that when the CS is traced on M, every node visited during this trace is recognized as some state of M and every transition of M is traversed. When the recognitions of the nodes in this trace are analyzed, it is observed that some of the nodes are recognized multiple times redundantly. This observation raises the following question: Is it possible to reduce the length of a given CS by eliminating redundant recognitions? In this thesis we focus on this question. We formalize the recognitions, detect multiple redundant recognitions and suggest a way to eliminate them to reduce the length of a given CS. An experimental study of our approach is also presented.

Item Type:Thesis
Uncontrolled Keywords:FSM based testing. -- Checking sequence. -- Random FSM generation. -- Boolean formula. -- SDM bazlı sınama. -- Kontrol dizileri. --- Rastlantısal SDM üretimi. -- İkili formül.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
ID Code:24715
Deposited By:IC-Cataloging
Deposited On:13 Oct 2014 16:53
Last Modified:25 Mar 2019 17:10

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