An efficient hardware architecture for H.264 adaptive deblocking filter algorithm

Parlak, Mustafa and Hamzaoğlu, İlker (2006) An efficient hardware architecture for H.264 adaptive deblocking filter algorithm. In: 1st NASA/ESA Conference on Adaptive Hardware and Systems, Istanbul, Turkey

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Official URL: http://ieeexplore.ieee.org/iel5/10912/34344/01638188.pdf?isnumber=34344&arnumber=1638188


This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 72 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can code 30 CIF frames (352x288) per second.

Item Type:Papers in Conference Proceedings
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
ID Code:1177
Deposited By:İlker Hamzaoğlu
Deposited On:17 Dec 2006 02:00
Last Modified:29 Apr 2016 15:24

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