A High performance and low power hardware architecture for H.264 cavlc algorithm
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Şahin, Esra and Hamzaoğlu, İlker (2005) A High performance and low power hardware architecture for H.264 cavlc algorithm. In: 13th European Signal Processing Conference, Antalya
In this paper, we present a high performance and low power hard-ware architecture for real-time implementation of Context Adap-tive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is im-plemented in Verilog HDL. The Verilog RTL code is verified to work at 76 MHz in a Xilinx Virtex II FPGA and it is verified to work at 233 MHz in a 0.18´ ASIC implementation. The FPGA and ASIC implementations can code 22 and 67 VGA frames (640x480) per second respectively.
|Item Type:||Papers in Conference Proceedings|
|Subjects:||Q Science > QA Mathematics|
|Deposited By:||İlker Hamzaoğlu|
|Deposited On:||17 Dec 2006 02:00|
|Last Modified:||29 Aug 2007 14:17|
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